This invention relates to an AFC (Automatic Frequency Control) circuit for matching the frequency of a reference clock signal in a mobile station to the frequency of a reference clock signal in a base station as a transmitting side.
In recent years, as a communication system used in mobile communication, attention is directed to a CDMA (Code Division Multiple Access) communication system resistant against interference and disturbance. In the CDMA communication system, communication is carried out as follows. On a transmitting side, a user signal to be transmitted is spread by the use of a spread code before it is transmitted. On a receiving side, despreading is carried out by the use of a spread code identical with the above-mentioned spread code to obtain the original user signal.
In the above-mentioned CDMA communication system, it is impossible to carry out despreading on the receiving side unless phase synchronization is established between spread code sequences on the transmitting side and the receiving side. Under the circumstances, in a mobile station as the receiving side, a TCXO (Temperature Compensated Crystal Oscillator) having very high frequency accuracy is used as a reference oscillator. The reference oscillator serves to generate a reference clock signal used upon demodulating a reception signal supplied from a base station as the transmitting side. However, since the mobile station is required to be small in size and low in cost, the reference oscillator used in the mobile station is relatively low in frequency accuracy as compared with that used in the base station. In this connection, the mobile station carries out an AFC operation for matching the frequency of the reference clock signal in the mobile station to the frequency of a reference clock signal in the base station.
Referring to FIG. 1, a conventional AFC circuit for carrying out the above-mentioned AFC operation will be described. The conventional AFC circuit is formed by a heterodyne receiver and comprises an antenna 1, a low-noise amplifier (LNA) 2, a down converter 3, an AGC (Automatic Gain Control) amplifier 4, a quadrature demodulator (DEM) 5, an A/D (Analog-to-Digital) converter 6, a PLL (Phase-Locked Loop) circuit 7, a reference clock generating circuit (TCXO) 8, an accumulator 9, a demodulating circuit 10, a frequency offset estimating circuit 51, a delay profile/search circuit 12, a CPU (Central Processing Unit) 53, and a timing generating circuit 54.
The low-noise amplifier 3 amplifies a reception signal received through the antenna 1 from a base station 300. The low-noise amplifier 3 thereby produces an amplified signal. The down converter 3 is supplied with the amplified signal from the low-noise amplifier 3 and converts the amplified signal into an intermediate frequency (IF) signal by the use of a first local signal 161. The AGC amplifier 4 is supplied with the IF signal from the down converter 3 and carries out gain control of the IF signal so that the A/D converter 6 has a constant input level. The AGC amplifier 4 delivers a gain-controlled IF signal to the quadrature demodulator 5.
Supplied with the gain-controlled IF signal, the quadrature demodulator 5 carries out quadrature demodulation by the use of a second local signal 162 to convert the gain-controlled IF signal into an analog baseband signal. Supplied with the analog baseband signal from the quadrature demodulator 5, the A/D converter 6 converts the analog baseband signal into a digital baseband signal.
The PLL circuit 7 is responsive to a reference clock signal generated by the TCXO 8 and produces the first local signal 161 to be supplied to the down converter 3 and the second local signal 162 to be supplied to the quadrature demodulator 5. The TCXO 8 produces the reference clock signal having an oscillation frequency controlled by a control voltage produced by the accumulator 9.
The delay profile/search circuit 12 is supplied with the digital baseband signal from the A/D converter 6 and produces profile data and a frame timing correction amount (xcex94t1). The profile data and the frame timing correction amount (xcex94t1) produced by the delay profile/search circuit 12 are shown in FIG. 2. The profile data represents a profile of data including in the digital baseband signal. It is noted here that the frame timing correction amount (xcex94t1) is a discrete value because it is derived from a sampling rate of the A/D converter 6.
The timing generating circuit 54 produces an ideal frame timing with reference to the reference clock signal from the TCXO 8 and adds to the ideal frame timing the frame timing correction amount (xcex94t1) produced by the delay profile/search circuit 12 to produce a frame timing signal 101 representative of the result of addition.
The demodulating circuit 10 comprises a RAKE receiver including a plurality of finger receivers and demodulates, with reference to the frame timing signal 101, the digital baseband signal produced by the A/D converter 6.
With reference to the frame timing signal 101, the frequency offset estimating circuit 51 calculates the frequency error contained in the digital baseband signal from the A/D converter 6. When the frequency error thus calculated becomes equal to or smaller than a predetermined value, the frequency offset estimating circuit 51 judges that the AFC operation is put in a locked state. When the frequency error becomes greater than the predetermined value, the frequency offset estimating circuit 51 judges that the AFC operation is put in an unlocked state. The frequency offset estimating circuit 51 informs the result of judgment to the CPU 53 by the use of a lock/unlock signal 106.
Referring to FIG. 3, description will be made of calculation of the frequency error in the frequency offset estimating circuit 51. The frequency error is calculated by the use of a symbol, such as a pilot symbol, having a symbol pattern which is preliminarily known on a receiver side. In FIG. 3, ideal symbol points 30 through 33 show symbols xe2x80x9c00xe2x80x9d, xe2x80x9c01xe2x80x9d, xe2x80x9c10xe2x80x9d, and xe2x80x9c11xe2x80x9d on an IQ plane in case where no frequency error is contained, respectively.
By way of example, consideration will be made about a signal modulated at 16 ksps by QPSK modulation. It is assumed that a pilot symbol at a particular timing has a symbol pattern xe2x80x9c00xe2x80x9d and that demodulation is carried out at a symbol point 20 obtained by rotation of xcex94xcex8=10xc2x0 on the IQ plane as illustrated in FIG. 3. In this event, the frequency error is calculated by:
16kxc3x9710xc2x0/360xc2x0=44 Hz.
Therefore, by feeding back the frequency error through the accumulator 9 to the TCXO 8, the AFC operation is put in the locked state, i.e., xcex94xcex8÷0xc2x0. Then, the frequency offset estimating circuit 51 produces a lock/unlock signal 106 representative of the locked state and delivers the lock/unlock signal 106 to the CPU 53.
Supplied with the lock/unlock signal 106, the CPU 53 knows the current state of the AFC operation.
The accumulator 9 produces a control voltage and adds to a current value of the control voltage the frequency error calculated by the frequency offset estimating circuit 51.
Referring to FIGS. 1 through 3, the operation of the conventional AFC circuit mentioned above will be described.
The reception signal received through the antenna 1 is amplified by the low-noise amplifier 2 and then converted by the down converter 3 into the IF signal by the use of the first local signal 16, produced by the PLL circuit 7. The IF signal is supplied to the AGC amplifier 4 to be gain-controlled so that the A/D converter 6 has a constant input level. The gain-controlled IF signal is supplied to the quadrature demodulator 5 to be quadrature-demodulated into the analog baseband signal by the use of the second local signal 162 produced by the PLL circuit 7. The analog baseband signal is supplied to the A/D converter 6 to be converted into the digital baseband signal. The digital baseband signal is supplied to the demodulating circuit 10, the frequency offset estimating circuit 51, and the delay profile/search circuit 12. Supplied with the digital baseband signal, the delay profile/search circuit 12 produces the profile data and the frame timing correction amount (xcex94t1).
The timing generating circuit 54 generates the ideal frame timing with reference to the reference clock signal from the TCXO 8. The timing generating circuit 54 adds to the ideal frame timing the frame timing correction amount (xcex94t1) produced by the delay profile/search circuit 12 to produce the frame timing signal 101 representative of the result of addition.
The frame timing signal 101 is supplied to the frequency offset estimating circuit 51 and the demodulating circuit 10. Supplied with the frame timing signal 101, the demodulating circuit 10 demodulates the digital baseband signal produced by the A/D converter 6.
Supplied with the frame timing signal 101, the frequency offset estimating circuit 51 calculates the frequency error contained in the digital baseband signal from the A/D converter 6.
The accumulator 9 produces the control voltage and adds to the current value of the control voltage the frequency error calculated by the frequency offset estimating circuit 51. The control voltage produced by the accumulator 9 is supplied to the TCXO 8 to control the frequency of the reference clock signal produced therefrom. Thus, feedback is carried out.
When the frequency error thus calculated becomes smaller than the predetermined value, the frequency offset estimating circuit 51 judges that the AFC operation is put in the locked state. When the frequency error becomes equal to or greater than the predetermined value, the frequency offset estimating circuit 51 judges that the AFC operation is put in the unlocked state. The result of judgment is informed to the CPU 53 by the use of the lock/unlock signal 106. Thus, the CPU 53 knows the current state of the AFC operation.
In the conventional AFC circuit described above, the frequency offset estimating circuit 51 calculates the frequency error, carries out frequency pulling operation in the AFC operation with reference to the frequency error thus calculated, and detects the locked and the unlocked states of the AFC operation by the use of the frequency error. Therefore, even if the AFC operation is in the locked state, the frequency offset estimating circuit 51 must continuously be operated in order to detect the unlocked state. This results in unnecessary power consumption.
The conventional AFC circuit mentioned above is disadvantageous in that unnecessary power consumption is inevitable because the frequency offset estimating circuit must continuously be operated to detect the unlocked state even if the AFC operation is in the locked state.
It is an object of this invention to provide an AFC circuit capable of reducing power consumption by stopping the operation of a frequency offset estimating circuit if an AFC operation is in a locked state.
It is another object of this invention to provide an AFC circuit capable of reducing power consumption by omitting the frequency offset estimating circuit.
According to an aspect of this invention, there is provided An AFC circuit for use in a receiver in matching the frequency of a reference clock signal in the receiver with the frequency of a reference clock signal in a transmitter, the circuit comprising:
an orthogonal demodulator supplied with a reception signal received from the transmitter for carrying out orthogonal demodulation by the use of a local signal to convert the reception signal into an analog baseband signal;
an A/D converter supplied with the analog baseband signal produced by the orthogonal demodulator for carrying out A/D conversion to produce a digital baseband signal;
a delay profile/search circuit responsive to the digital baseband signal produced by the A/D converter for producing profile data represents profile of data of the digital baseband signal and a frame timing correction amount, the profile data representing a profile of data including in the digital baseband signal;
a timing generating circuit for generating an ideal frame timing on the basis of the reference clock signal in the receiver and for adding the frame timing correction amount to the ideal frame timing to produce a frame timing signal, the timing generating circuit being furthermore for calculating, with reference to the frame timing correction amount, a first frequency error representative of a difference in frequency between the reference clock signal in the receiver and the reference clock signal in the transmitter and for judging that an AFC operation is put into an unlocked state to produce an unlock signal if an absolute value of the first frequency error becomes equal to or greater than a first predetermined value;
a frequency offset estimating circuit for calculating, with reference to the frame timing signal, a second frequency error representative of a difference in frequency between the reference clock signal in the receiver and that reference clock signal in the transmitter which is contained in the digital baseband signal from the A/D converter, the frequency offset estimating circuit being furthermore for judging that the AFC operation is put into a locked state to produce a lock signal if an absolute value of the second frequency error becomes equal to or smaller than a second predetermined value not greater than the first predetermined value, the frequency offset estimating circuit being turned off and on under control of a control signal;
a CPU for controlling the frequency offset estimating circuit by the use of the control signal so that the frequency offset estimating circuit is turned off when the CPU is supplied with the lock signal and that the frequency offset estimating circuit is turned on when the CPU is supplied with the unlock signal;
an accumulator which produces a control voltage and which is for adding to a current value of the control voltage the frequency error calculated by the frequency offset estimating circuit to produce a new value of the control voltage;
a reference clock generating circuit for generating, as the reference clock signal in the receiver, a controlled reference clock signal having an oscillation frequency controlled by the new value of the control voltage; and
a PLL circuit for producing the local signal on the basis-of the controlled reference clock signal.
In the AFC circuit according to this invention, the frequency offset estimating circuit detects the locked state of the AFC operation when the detected frequency error is substantially equal to 0. In this event, the CPU produces the control signal to make the frequency offset estimating circuit stop its operation. The timing generating circuit is responsive to the frame timing correction amount from the delay profile/search circuit and calculates the frequency error. If the frequency error becomes equal to or greater than the predetermined value, the timing generating circuit produces the unlock signal. Then, the CPU produces the control signal to make the frequency offset estimating circuit start its operation. Thus, the AFC operation is carried out.
Therefore, it is unnecessary to continuously keep the frequency offset estimating circuit in operation in order to detect the unlocked state of the AFC operation and to carry out the AFC operation. The operation of the frequency offset estimating circuit can be stopped during the locked state of the AFC operation. Therefore, power consumption can be reduced.
According to another aspect of this invention, there is provided an AFC circuit for use in a receiver in matching the frequency of a reference clock signal in the receiver with the frequency of a reference clock signal in a transmitter, the circuit comprising:
an orthogonal demodulator supplied with a reception signal received from the transmitter for carrying out orthogonal demodulation by the use of a local signal to convert the reception signal into an analog baseband signal;
an A/D converter supplied with the analog baseband signal produced by the orthogonal demodulator for carrying out A/D conversion to produce a digital baseband signal;
a delay profile/search circuit responsive to the digital baseband signal produced by the A/D converter for producing profile data represents profile of data of the digital baseband signal and a frame timing correction amount, the profile data representing a profile of data including in the digital baseband signal;
a timing generating circuit for generating an ideal frame timing on the basis of the reference clock signal in the receiver and for adding the frame timing correction amount to the ideal frame timing to produce a frame timing signal for use in demodulating the digital baseband signal, the timing generating circuit being furthermore for calculating, with reference to the frame timing correction amount, a frequency error representative of a difference in frequency between the reference clock signal in the receiver and the reference clock signal in the transmitter and for judging that an AFC operation is put into an unlocked state to produce an unlock signal if an absolute value of the frequency error becomes equal to or greater than a predetermined value, the timing generating circuit judging that the AFC operation is put into a locked state to produce a lock signal if the frequency error becomes smaller than the predetermined value;
a logical table memorizing section which memorizes a table of the frequency error based on the frame timing correction amount and which is supplied with a particular frame timing correction amount calculated by the delay profile/search circuit for calculating a particular frequency error corresponding to the particular frame timing correction amount supplied thereto;
an accumulator which produces a control voltage and which is for adding to a current value of the control voltage the frequency error calculated by the logical table memorizing section to produce a new value of the control voltage;
a reference clock generating circuit for generating, as the reference clock signal in the receiver, a controlled reference clock signal having an oscillation frequency controlled by the new value of the control voltage; and
a PLL circuit for producing the local signal on the basis of the controlled reference clock signal.
In this invention, the frequency offset estimating circuit can be omitted by providing the logical table memorizing section which memorizes the table of the frequency error based on the frame timing correction amount. Thus, power consumption can be reduced not only during the stop of the AFC operation but also during execution of the AFC operation.